As for semi-conductor devices on ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), there is a phenomenon that different outputs are obtained from devices of the same kind on which the same circuits are mounted because each device has different device characteristics such as gate delays. A circuit that produces such a phenomenon and its technology are called Physical Unclonable Function and Physical Uncloning Technique (hereafter, referred to as PUF) or the like. PUF is expected to be applied to authentication, encryption and such.
Non-patent literature 1 describes an example of PUF. In Non-Patent Literature 1, a glitch which occurs in an output signal in a combination circuit is exploited. FIGS. 14 and 15 illustrate the principle of the PUF (referred to as glitch PUF) in Non-Patent Literature 1. The glitch PUF of Non-Patent Literature 1 is discussed with reference to FIGS. 14 and 15. A glitch is a phenomenon that the value of a signal repeatedly changes between 0 and 1 before the signal settles to its intended value. Referring to FIG. 14, when the values of input signals x1 to xL to a random logic 201 in a combination circuit are varied, the values of output signals y1 to yM (and the value of a signal g selected from among the output signals) change accordingly. Such a change does not occur instantly, but takes a certain period of time. In a transitional state of the change, a glitch in which a value repeatedly changes between 0 and 1 occurs, as shown in an area 202.
The glitch shape is determined by delays in gates in the random logic 201. Gate delays vary from device to device, and therefore the glitch shape differs depending on the device. Therefore, by allocating the glitch shape to 0 or 1, a device unique information bit can be generated. Non-patent Literature 1 describes a method of converting the parity of the number of pulses included in a glitch into a bit, as shown in (a) and (b) in FIG. 15. That is the principle of the glitch PUF.
Referring to Non-Patent Literature 1, to acquire the glitch shape, a signal (hereafter, referred to as glitch signal) including a glitch is sampled to acquire a waveform (hereafter, referred to as glitch waveform) including the glitch. A glitch is a phenomenon occurring in a shorter period of time than a clock cycle. For this reason, the following process is required:    (a) one glitch signal is sampled by slightly phase-shifted N clocks; or    (b) slight-delay added N glitch signals are sampled by one clock.
The “slight delay” is a period of time (delay) that is shorter than the interval between pulses included in a glitch. Non-Patent Literature 1 is based on the latter (b) (FIG. 16). Non-Patent Literature 1 also proposes a method of using wires for carry bits in an adder circuit in which delay is suppressed to a minimum, on LSI such as FPGA, as a method of adding the “slight delay”.